ADF4108 pdf datasheet PLL Frequency Synthesizer

赵城藏软件站机械电子分类下的ADF4108 pdf datasheet PLL Frequency Synthesizer，文件大小为289KB，适用系统为Vista, Win2003, WinXP, Win2000, NT，以下为介绍或使用方法。

The ADF4108 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REF_IN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth (8GHz) means that frequency doublers or prescalers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.