ADF4001 pdf datasheet 200MHz Clock Generator PLL

赵城藏软件站机械电子分类下的ADF4001 pdf datasheet 200MHz Clock Generator PLL，文件大小为258KB，适用系统为Vista, Win2003, WinXP, Win2000, NT，以下为介绍或使用方法。

The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation.