AD9540 pdf datasheet Low Jitter DDS-based Clock Generator an

赵城藏软件站机械电子分类下的AD9540 pdf datasheet Low Jitter DDS-based Clock Generator an，文件大小为469KB，适用系统为Vista, Win2003, WinXP, Win2000, NT，以下为介绍或使用方法。

The AD9540 supports a variety of functions including signal synthesis and low jitter clock generation useful in a wide variety of applications. The device features high performance PLL circuitry including a flexible 200 MHz Phase Frequency Detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CML mode (PECL compatible) output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported. An onboard 400 MSPS DDS provides extremely fine tuning resolution and phase programmability. Information is loaded into the AD9540 via a serial I/O port which has a device write speed of 25Mbit/sec. The AD9540 frequency divider block can also be programmed to support a spread spectrum clocking mode.

The AD9540 is specified to operate over the extended automotive range of -40°C to +85°C.