ADN2819 pdf datasheet Multi Rate Limiting Amplifier and Clock

赵城藏软件站机械电子分类下的ADN2819 pdf datasheet Multi Rate Limiting Amplifier and Clock，文件大小为123KB，适用系统为Vista, Win2003, WinXP, Win2000, NT，以下为介绍或使用方法。

The ADN2819 provides receiver functions of Quantization, Signal Level Detect and Clock and Data Recovery at rates of OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All SONET jitter requirements are met, including: Jitter Transfer; Jitter Generation; and Jitter Tolerance. All specifications are quoted for -40ºC to +85ºC ambient temperature unless otherwise noted.

The proprietary delay and phase-locked loop design of the ADN2819 provides unprecedented jitter performance for robust high-speed networking designs.

The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip crystal oscillator. Both native rates and 15/14 rate digital wrappers rates are supported by the ADN2819, without any change of reference clock required. This device together with a PIN diode and a TIA preamplifier can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold.